1. Field of the Invention
The present invention generally relates to Random Access Memory (RAM) bus architectures and, more particularly, to a RAM bus architecture that utilizes standard Synchronous Dynamic RAMs (SDRAMs) and that is capable of high bandwidth, high speed data transfer while minimizing Input/Output (I/O) pin count.
2. Background Description
High bandwidth architectures have been proposed for Dynamic Random Access Memories (DRAMs) that reduce chip pin count to nine pins by multiplexing input commands, addresses and data. For example, see U.S. Pat. No. 5,430,676 to Ware et al., entitled "Dynamic Random Access Memory System," U.S. Pat. No. 5,434,817 to Ware et al., entitled "Dynamic Random Access Memory System," and U.S. Pat. No. 5,511,024 to Ware et al., entitled "Dynamic Random Access Memory System."
In these high bandwidth DRAM architectures, commands are serially input on the nine pins at a 553 MHZ clock rate. Packets of control information called "Request Packets" are transferred to and stored in the DRAM during what is termed a transaction operation. After a pre-specified latency period, data is either input or output at a 500 MHZ transfer rate.
Request packets include a device, bank, and row address of a page to be activated; the column address of the first of eight bytes (an octo-byte) to be read; and, a Data packet. A Data packet includes input data and data masking commands.
Bus switching rates during these command or data transactions place stringent requirements on system bus net. Since all system communication and handshaking with the DRAM is through the nine bit bus, parallel system operations become difficult. Although the high bandwidth architecture may provide a faster data transfer rate than other high bandwidth RAM alternatives, bus contentions and bus blocking may result to reduce overall system performance and prevent seamless data transfers.